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FEATURES Integrated Front End for Single Pair or Two Pair HDSL Systems Meets ETSI Specifications Supports 1168 Kbps and 2.32 Mbps Transmit and Receive Signal Path Functions Receive Hybrid Amplifier, PGA and ADC Transmit DAC, Filter and Differential Outputs Programmable Filters Control and Ancillary Functions Timing Recovery DAC Normal Loopback and Low Power Modes Simple Interface-to-Digital Transceivers Single 5 V Power Supply Power Consumption: 320 mW--(Excluding Driver) Package: 80-Lead MQFP Operating Temperature: -40 C to +85 C
2 Pair/1 Pair ETSI Compatible HDSL Analog Front End AD6472
GENERAL DESCRIPTION
The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is designed to support industry standard digital transceivers. While providing the full analog front end for ETSI standards (two pair or single pair HDSL applications) the AD6472 supports other applications because the architecture allows for bypassing the functional blocks. The normal, low power, and loopback modes and the digital interface combine to make the AD6472 simple to integrate into systems.
FUNCTIONAL BLOCK DIAGRAM
TX_GAIN
12-BIT DAC
2 ANALOG FILTER 2 2
DRIVER
TX 2
TO VCXO
7-BIT DAC
AD6472
CONTROL LOGIC BUFFER 12-BIT ADC 2 2 2 ANALOG FILTER 2 PGA 3 2 HYBRID CIRCUIT RX
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD6472-SPECIFICATIONS (T = T
A
MIN
to TMAX unless otherwise noted)
Max Units dB dB 18.688 MHz Bits kHz V p-p Diff kHz kHz % dB dB V dBm V p-p Diff V p-p Diff V p-p Diff dB dB VCM = 2.5 V. See Figure 3 5 V p-p Diff k Condition -6 dB to +9 dB dB dB dB kHz kHz % Bits V V V V V V V V V V V mA mA mA mA +85 C MODE_SEL1 = 0 MODE_SEL1 = 1 Condition The complete transmit path spectrum and pulse shape comply with ETSI requirements. The transmit DAC maximum update rate is half the maximum output data rate, i.e., 1168 kHz. The maximum transmit clock is 16 x 1168 = 18.688 MHz.
Parameter
TRANSMIT CHANNEL SNR THD TRANSMIT DAC Clock Frequency Resolution Update Rate Output Voltage TRANSMIT FILTER Corner Frequency (3 dB)1 Accuracy Gain LINE DRIVER VCM Output Power Output Voltage TRANSMIT VOLTAGE LEVEL RECEIVE CHANNEL SNR THD HYBRID INTERFACE Input Voltage Range Input Impedance PROGRAMMABLE GAIN AMPLIFIER Overall Gain Accuracy Gain Step Gain Step Accuracy RECEIVE FILTER Corner Frequency (-3 dB)1 Accuracy TIMING RECOVERY DAC Resolution Output Low Output High DIGITAL INTERFACE Input Logic High, VIH Input Logic LOW, VIL Output Logic High, VOH Output Logic Low, VOL Input Logic High, VIH Input Logic Low, VIL Output Logic High, VOH POWER SUPPLY VOLTAGE
Min 68 66
Typ 71 71
12 1168 2 320 535 5 9.53 3.53 2.5 13.5 6 6 3 68 66 71 71
10
MODE_SEL1 = 0 MODE_SEL1 = 1
Transformer Turns Ratio = 1:2.3 at 50 kHz When Loaded by ETSI (RTR/TM3036) HDSL Test Loops TX_GAIN = 0 TX_GAIN = 1
10 1 3 0.25 320 640 5 7 0.5 4.5 3.3 0.8 VDD - 0.3 0.4 2.0 0.2 VDD - 0.3 4.75 3.15 5 3.3 65 73 50 17 -40 5.25 3.45
10
Guaranteed Monotonic
5 V Supply, VMIN to VMAX
3.3 V Supply, VMIN to VMAX
VMIN to VMAX 5 V Supply 3.3 V Supply VMIN to VMAX, TMIN to TMAX 5 V Supply, MODE_SEL1 = 0 5 V Supply, MODE_SEL1 = 1, MODE_SEL0 = 1 With 50 Differential Load TMIN to TMAX
POWER SUPPLY CURRENT Normal Mode, Excl. Driver OVRSAMP Mode Line Driver Low Power Mode OPERATING TEMPERATURE RANGE
NOTES 1 The ADC clock period t(1/ f) is used for the dynamic tuning of the Tx and Rx filters. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6.0 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Operating Temperature Range (Ambient) . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) MQFP . . . . . . . . . . . . . . . . +280C
*Stresses above those listed in this section may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
80-Lead Plastic Quad Flatpack Package . . . . . . . JA = 45C/W
ORDERING GUIDE
Model AD6472BS
Temperature Range -40C to +85C
Package Description 80-Lead Plastic Quad Flatpack
PIN CONFIGURATION
TR_DAC_OUT +3V_DVDD DGND +3V_DVDD
Package Option S-80A
RXCLK
RX11 RX10
RX9 RX8
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
+5V_DVDD 1 DGND 2 MODE_SEL0 3 MODE_SEL1 4 AA_FLTR_BP 5 PWRDN 6 NC 7 TX_GAIN_SEL 8 TX_DRVR_BP 9 ADC_BUF_BP 10 TX_LPF_BP 11 TSTGND 12 LOOPBACK 13 DGND 14 +3V_DVDD 15 TX_DATA 16 TX_SYNC 17 TX_CLK 18 +5V_DVDD 19 DGND 20
RX7 RX6
RX5 RX4 RX3
RX2 RX1
SFRAME SDATA
RX0 SCLK
PIN 1 IDENTIFIER
60 NC 59 +5V_DVDD 58 DGND 57 AVDD 56 AGND 55 CM_LVL 54 VREF
AD6472
S-80A
TOP VIEW (Not to Scale)
53 CAP_BOT 52 CAP_TOP 51 REF_COM 50 ADC_INA 49 ADC_INB 48 AA_FLTR_OUTA 47 AA_FLTR_OUTB 46 PGA_GC0 45 PGA_GC1 44 PGA_GC2 43 AVDD 42 AGND 41 HYB_IN1_A
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
TX_IOUT_A TX_IOUT_B
IOUT_SET NC
CAP_B CAP_C
NC
TX_LPF_OUT_A AVDD
DRVR_OUT_B DRVR_OUT_A
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6472 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TX_LPF_IN_B TX_LPF_IN_A TX_LPF_OUT_B
AGND HYB_IN2_B
HYB_IN2_A HYB_IN1_B
AGND AVDD
WARNING!
ESD SENSITIVE DEVICE
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AD6472
PIN CONFIGURATIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Mnemonic +5 V_DVDD DGND MODE_SEL0 MODE_SEL1 AA_FLTR_BP PWRDN NC TX_GAIN_SEL TX_DRVR_BP ADC_BUF_BP TX_LPF_BP TSTGND LOOPBACK DGND +3 V_DVDD TX_DATA TX_SYNC TX_CLK +5 V_DVDD DGND NC IOUT_SET
Description
Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Mnemonic HYB_IN1_A AGND AVDD PGA_GC2 PGA_GC1 PGA_GC0 AA_FLTR_OUTB
Description
+5 V Digital Supply. Digital Ground. Bit Rate--Filter Corner Select. Bit Rate--Filter Corner Select. Antialiasing Filter Bypass. Power-Down Active Low. No Connect. Transmit Attenuation (6 dB) Select. Transmit Driver Bypass. ADC Buffer Bypass. Transmit Filter Bypass. Factory test pin. Connect to DGND. Loopback Select. Digital Ground. +3.3 V Digital Supply. Transmit Data Input. Transmit Data Frame Sync Input. Transmit Clock Input. +5 V Digital Supply. Digital Ground. No Connect. DAC Output Current Full Scale (With Resistor to Ground). NC No Connect. CAP_B Decoupling Pin for Internal Node. CAP_C Decoupling Pin for Internal Node. TX_IOUT_A TXDAC Complementary Current Output. TX_IOUT_B TXDAC Complementary Current Output. AGND Analog Ground. AVDD +5 V Analog Supply. TX_LPF_IN_B Differential Input to LPF. TX_LPF_IN_A Differential Input to LPF. TX_LPF_OUT_B Differential Output from Transmit (If Driver Bypassed). TX_LPF_OUT_A Differential Output from Transmit (If Driver Bypassed). AVDD +5 V Analog Supply. DRVR_OUT_B Differential Driver Output. DRVR_OUT_A Differential Driver Output. AGND Analog Ground. HYB_IN2_B Hybrid Noninverting Input. HYB_IN2_A Hybrid Noninverting Input. HYB_IN1_B Hybrid Inverting Input.
Hybrid Inverting Input. Analog Ground. +5 V Analog Supply. PGA Gain Select Bits. PGA Gain Select Bits. PGA Gain Select Bits. Differential Output of the Antialiasing Filter. AA_FLTR_OUTA Differential Output of the Antialiasing Filter. ADC_INB Differential Input to the ADC. ADC_INA Differential Input to the ADC. REF_COM Reference Common. CAP_TOP Decoupling Pin for ADC Reference. CAP_BOT Decoupling Pin for ADC Reference. VREF External Voltage Reference. CM_LVL Common-Mode Level. (1/2 Supply Voltage, Nominally.) AGND Analog Ground. AVDD +5 V Analog Supply. DGND Digital Ground. +5 V_ DVDD +5 V Digital Supply. NC No Connect. +3 V_ DVDD +3 V Digital Supply. TR_DAC_OUT Timing Recovery DAC Output Voltage. SDATA Serial Data Input to Timing Recovery DAC. SFRAME Frame Sync for Timing Recovery. SCLK Clock for Timing Recovery DAC. Serial Data. RX0 Digital Output Data. RX1 Digital Output Data. RX2 Digital Output Data. RX3 Digital Output Data. RX4 Digital Output Data. RX5 Digital Output Data. DGND Digital Ground. +3 V_DVDD +3 V Digital Supply. RX6 Digital Output Data. RX7 Digital Output Data. RX8 Digital Output Data. RX9 Digital Output Data. RX10 Digital Output Data. RX11 Digital Output Data. RXCLK Clock Input for ADC Data.
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AD6472
Circuit Description
The AD6472 is an HDSL analog front end for either 2-pair or single pair applications.
Transmit Channel
The AD6472 receives, from a DSP transceiver core, a serial 2s complement data stream. The data are 16-bit words and the MSB is received first. The 12-bit DAC converts the digital data to an analog signal. Although HDSL uses four level 2B1Q modulation, the 12-bit DAC is necessary because of the linearity requirements of the echo canceling circuit. The active filters have dynamic tuning and selectable filter corners that meet transmit mask requirements for both two-pair and single pair applications. A 6 dB attenuation option is included as part of the filter to increase the driver output dynamic range. Bypassing the active filter means giving up the 6 dB option, and reduces the maximum TX output voltage to 2 V p-p diff.
-0.4T B C D
The filtered transmit signal is then processed by the driver amplifier. The DAC output controls the driver output level. The designer can choose to bypass the driver amplifier; in this case the driver amplifier will be powered down, and the TX output will be at the TX_LPF_OUT pins. The AD6472 meets the requirements of the ETSI masks (both frequency and time domains for pulse shape). This includes the worst case in RTR/TM 3036.
Table I. Transmit Spectra
Rate Kbps 1168 2320
Application
Nyquist Frequency kHz
Time Interval T ( s) 1710 862
2-Pair E1 292 Single Pair E1 580
0.4T
PARAMETER A B C D E F G H
VALUE 0.0264 2.8248 2.64 2.4552 0.0792 -0.0264 -0.4224 -0.1320 E
% 1 107 100 93 3 -1 -16 -5
1.25T
A F H G -1.2T -0.6T 0 0.5T 14T 50T
A F
Figure 1. 2-pair Transmit Pulse Shape Mask Normalized
-0.4T B C D
0.4T
PARAMETER A B C D E F G H
VALUE 0.0250 2.6750 2.500 2.3250 0.104 -0.0250 -0.5000 -1.250 E
% 1 107 100 93 4 -1 -20 -5
1.25T
A F H G -1.2T -0.6T 0 0.5T 14T 50T
A F
Figure 2. Single Pair Transmit Pulse Shape Mask Normalized
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AD6472
Receive Channel Hybrid Amplifier Transmit and Receive Filters
The hybrid amplifier performs balanced to unbalanced conversion.
Programmable Gain Amplifier (PGA)
Refer to Table III for transmit and receive channels filter control information. The receive channel filters meet ETSI requirements.
Analog-to-Digital Converter (ADC)
The PGA can be programmed to amplify the receive signal from between -6 dB and 9 dB. Refer to Table II for PGA gain control information.
10k HYB_IN1_A HYB_IN1_B HYB_IN2_A HYB_IN2_B 10k 10k 10k 10k 10k TO PGA
The receive channel ADC has a pipeline architecture with 12bit resolution. The ADC can be clocked at 2320 kHz, maximum. Output data is provided in 2s complement form.
Timing Recovery D/A
The AD6472 has an integrated D/A converter to control an external VCXO used for timing recovery. The D/A is 7 bits and monotonic. The D/A accepts 7 bits inverted format input data serially with the MSB first.
Configuration Control
Figure 3.
Table IV presents control information that you use to configure the AD6472.
Table II.
PGA_GC2 0 0 0 0 1 1 1 1
Gain Control Bit PGA_GC1 0 0 1 1 0 0 1 1
Table III.
PGA_GC0 0 1 0 1 0 1 0 1
Binary Count GAIN (dB) -6 -3 0 3 6 9 9 9
Receive Channel MODE_SEL1 0 0 1 1
Filter Control Bit MODE_SEL0 0 1 0 1
Receive Clock Frequency (kHz) 1168/2 Reserved 1160 1160 x 2
3 dB Frequency (kHz) Rx = 320/Tx = 320 Reserved Rx = 640/Tx = 535 Rx = 640/Tx = 535
Table IV. Configuration Control
Pin 5 6 7 8 9 11 13
Mnemonic AA_FLTR_BP PWRDN ADC_BUF_BP TX_GAIN_SEL TX_DRVR_BP TX_LPF_BP LOOPBACK
Logic 0 = Function Receive Filter in Circuit Low Power Selected ADC Buffer in Circuit 0 dB Attenuation Line Driver in Circuit Transmit Filter in Circuit Normal Operation
Logic 1 = Function Receive Filter Bypassed Normal Operating Mode ADC Buffer Bypassed 6 dB Attenuation Line Driver Bypassed Transmit Circuit Bypassed Analog Loopback Selected
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AD6472
S1 S2 S3 S4
ANALOG INPUT
tC t CH t CL
INPUT CLOCK RXCLK
tOD
OUTPUT DATA RX11:RX0
DATA1
Figure 4. Receive Interface Timing Diagram
Receive Interface Timing Table VI. 40% to 60% Duty Cycle RXCLK Clock when the RXCLK = 1160 kHz Symbol tC tCH tCL tOD Latency Parameter Clock Period Clock Pulsewidth High Clock Pulsewidth Low Output Delay Pipeline Delay Min Typ 862 342 514 8 3 514 342 19 3 Max Units ns ns ns ns Cycles
The analog input is sampled at the rising edge of the RXCLK. The digital data, RX11:RX0, is valid on each falling edge of RXCLK. Figure 4 shows a three-cycle latency on the receive data. Table V through Table VII lists the RXCLK clock switching specifications for various RXCLK conditions. See Table IV, Configuration Control.
Table V. 40% to 60% Duty Cycle when the RXCLK = 1168 / 2 kHz Symbol tC tCH tCL tOD Latency Parameter Clock Period Clock Pulsewidth High Clock Pulsewidth Low Output Delay Pipeline Delay Min Typ 1712 685 1027 8 13 3 3 Max 1027 685 19 3 Units ns ns ns ns Cycles
13 3
Table VII. 40% to 60% Duty Cycle RXCLK when the RXCLK = 1160 2 kHz Symbol tC tCH tCL tOD Latency Parameter Clock Period Clock Pulsewidth High Clock Pulsewidth Low Output Delay Pipeline Delay Min Typ 431 171 257 8 3 257 171 19 3 Max Units ns ns ns ns Cycles
13 3
tSU tH
TX_CLK
12ns 10ns
2 1
TX_SYNC
TX_DATA
D11 MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
D11 MSB
D10
D9
1. THE RISING EDGE TO TX_SYNC CAN OCCUR ANYWHERE. TX_SYNC MUST BE AT LEAST ONE CLOCK CYCLE WIDE. 2. TX_SYNC FALLING EDGE MUST OCCUR AFTER THE TX_CLK RISING EDGE THAT CAPTURED THE SERIAL LSB. THIS ENSURES CORRECT LOADING INTO THE DAC. THE FIRST 12 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TX PATH DAC, MSB FIRST. THE NUMBER SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS: OUTPUT FULL SCALE 1/2 FULL SCALE 1/2 FULL SCALE MINUS 1LSB ZERO WORD 011111111111 000000000000 111111111111 100000000000
Figure 5. Transmit Interface Timing Diagram
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AD6472
tSU tH
SCLK 12ns 10ns
2
SFRAME
SDATA
D6 MSB
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
D6 MSB
D5
D4
1. THE RISING EDGE OF SFRAME CAN OCCUR ANYWHERE. SFRAME MUST BE AT LEAST ONE CLOCK CYCLE WIDE. 2. SFRAME FALLING EDGE MUST OCCUR BEFORE THE SCLK RISING EDGE THAT CAPTURED THE SERIAL LSB. THIS ENSURES CORRECT LOADING INTO THE DAC. THE FIRST 7 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TR DAC, MSB FIRST. THE NUMBER SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS: OUTPUT FULL SCALE MID-SCALE MINIMUM WORD 1111111 1000000 0000000 VOLTAGE 4.5 2.5 0.5
Figure 6. Timing Recovery DAC Converter Timing
PCB Layout Recommendations
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Analog and Digital Ground Planes
Separate the analog and digital grounds. Use a single 35 to 50 mil wide trace under the device to connect the two ground planes. Connect the IC ground pins directly to the respective ground planes. Use one 0.1 F capacitor for each IC decoupling power supply connection in addition to capacitance shown in schematic.
80-Lead Metric Plastic Quad Flatpack S-80A
0.690 (17.45) 0.667 (16.95) 0.555 (14.10) 0.547 (13.90) 0.486 (12.35) BSC
80 1 61 60
Power Supply Capacitors
0.134 (3.40) MAX 0.041 (1.03) 0.029 (0.73) SEATING PLANE
TOP VIEW
(PINS DOWN)
0.004 (0.10) MAX 0.010 (0.25) MIN 0.120 (3.05) 0.100 (2.55)
20 21
41 40
0.026 (0.65) BSC
0.015 (0.38) 0.009 (0.22)
0.486 (12.35) BSC 0.555 (14.10) 0.547 (13.90) 0.690 (17.45 0.667 (16.95)
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PRINTED IN U.S.A.
C3302-8-4/98
1

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